CMOL-Based Resistive Memory Architectures

Summary

We have shown that the CMOL concept may enable terabit-scale resistive memories with transistor-free cells. Our first architecture for such memories [1] was not very successful, because it required a very low fraction (<0.1%) of defective crosspoint devices. However, combining a new memory hardware architecture with more advanced error-correction codes we have been able to increase [2] the calculated defect-tolerance rather dramatically (up to ~10% for stuck-at-open faults).

Publications

1. D. B. Strukov and K. K. Likharev, "Prospects for Terabit-scale Nanoelectronic Memories", Nanotechnology vol. 16, No. 1, pp. 137-148 (Jan. 2005).

2. D. B. Strukov and K. K. Likharev, "Defect-tolerant Architectures for Nanoelectronic Crossbar Memories", Journal of Nanoscience and Nanotechnology, vol. 7, No. 1, pp. 151-167 (Jan. 2007).

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