Nanoscale MOSFETs
Summary
We are exploring more and more refined
models of nanoscale field-effect transistors, with the general goal to
determine the ultimate scaling limits for this workhorse components of silicon integrated
circuits. While our first models have ignored the major parasitic effect of
source-to-drain tunneling altogether [1] or used the simple WKB approximation
for the description of this effect [2, 3], more recent versions of the theory
[4-6] are based on the joint solution of the 1D Schrödinger equation with 2D
Poisson equation. The results show that while advanced Si MOSFETs may provide
voltage gain even at channel length as small as 2 nm (~8 silicon atoms long),
below ~10 nm virtually all their characteristics (notably the threshold value
of the gate voltage) become increasingly sensitive to random variation of
device parameters including all geometrical dimensions.
Publications
1. F. Pikus and K.
Likharev, "Nanoscale
field-effect transistors: An ultimate size analysis", Appl.
Phys. Lett., vol. 71, pp. 3661-3663, Dec. 1997.
2. Y.
Naveh, A. Korotkov, and K. Likharev, "Shot-noise suppression in multimode ballistic Fermi conductors",
Phys. Rev. B, vol. 60, pp. R2169-2172, July 1999.
3. Y.
Naveh and K. Likharev, "Modeling
of 10-nm-scale ballistic MOSFET's", IEEE Electron.
Device Lett., vol. 21, pp. 242-244, May 2000.
4. V. A. Sverdlov, T.
J. Walls, and K. K. Likharev, “Nanoscale Silicon MOSFETs: A theoretical study”,
IEEE Trans. on Electron Devices, vol. 50, pp. 1926-1933, Sept. 2003.
5. T. J. Walls, V. A.
Sverdlov, and K. K. Likharev, “Nanoscale SOI MOSFETs: A comparison
of two options”, Solid State Electronics, vol. 48, pp.
857-865, 2004.
6. J. B. Li, T. J.
Walls, and K. K. Likharev, "Nanoscale SOI MOSFETs: In search for the best geometry",
in: SOI Technology and Devices XII, ed. by G. K. Celler, ECS, Pennington,
NJ, 2005, pp. 11-20.
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